Edward Yi Chang
National Chiao Tung University, Taiwan
Title: Nano scale InGaAs FinFET for post Si CMOS application
Biography
Biography: Edward Yi Chang
Abstract
To meet Moore’s law, the academia and industry have worked rigorously to develop advanced technologies in order to reach the ITRS roadmap standard. However, as the devices are reaching their physical limits, we are facing challenges; two most effectively ways to keep the device scaling are either using different transistor architectures or using advanced high mobility channels. Among many III-V compound semiconductors, InxGa1-xAs materials are the most promising candidates as high electron mobility channels for scaling CMOS devices to satisfy the quest of future logic applications. Besides, high-k materials, owning to its high permittivity is very critical material for integrating with III-V semiconductors in sub-nanometer technology regions. Unfortunately, inherently poor quality of high-k/III-V interfaces, which degrades the gate controllability and the channel mobility, has not been overcome yet. To achieve high efficiency and low power consumption high-k/III-V MOS devices, the MOS structures should have high interface quality in conjunction with a suitable and reliable dielectric gate stack. In addition, the gate metals must have effective work functions aligned with the band edges of the channel materials, as well as a small work function variation. This talk focuses on the metal/high-k/InGaAs interface study and several new results of the InGaAs FinFETs will be presented which can be the key technologies for next generation InGaAs channel based CMOS
technology.